Microelectronic integrated circuits (ICs) based on patterned semiconductor materials are continuing to evolve towards devices with an extremely high density of circuit elements per unit volume. The use of copper (Cu), with twice the conductivity of aluminum and three times the conductivity of tungsten, has been replaced as the interconnect material in advanced ICs manufacture using either single inlay or dual damascene processes. The conventional method of patterning trenches in a via-first dual damascene process involves filling via openings with an organic bottom anti-reflective coating (BARC), applying a photoresist layer on the via plug and then performing trench lithography, but a large filling bias between the isolated and dense (iso-dense) via plugs is usually observed. It is always challenging to optimize the subsequent trench recipe due to uneven filling of the iso-dense via plugs, thus the trench is incompletely etched leaving a fence of unetched resinous material around the via plug. In one approach to the problem of step height differences in the iso-dense via plugs, an extra step of etch back is needed to minimize the iso-dense via filling variation of organic materials, but complex procedures and high process costs are accompanied. U.S. Pat. No. 6,645,851 to Ho et al, describing a method of forming a planarized photoresist coating on contact holes with different duty ratios, is incorporated herein by reference.